1. Field of the Invention
This invention relates to circuits an integrated circuit that provide protection from electrostatic discharge (ESD) events. More particularly, this invention relates to circuits that will prevent a differential voltage level between two different power supply voltage terminals from exceeding a specified voltage level and thus prevent damage to the integrated circuit.
2. Description of the Related Art
Application specific integrated circuits (ASIC) often have either multiple pads connected to a single power supply voltage source or multiple isolated power supply voltage sources. FIG. 1 shows a model power supply distribution system similar to that described in xe2x80x9cDesigning On-Chip Power Supply Coupling Diodes for ESD Protection and Noise Immunity,xe2x80x9d S. Dabral et al., Proceedings of EOS/ESD Symposium, 1993, pp. 5B.6.1-5B.6.11.
A power supply voltage source is connected through a distribution system between the Vcc pads 100 and 102 and the Vss pads 120 and 122. The structure of the ASIC shows a core logic section 110 and a peripheral logic section 138. In order to isolate noise, such as caused by simultaneous switching of driver circuits in the peripheral logic section 138 or impedance mismatch on transmission line connected to the I/O pad 136, the peripheral logic section 138 has a separate power supply distribution network from that of the core logic section 110.
The distribution of the power supply voltage Vcc through the Vcc pad 100 is modeled by the resistor RVcc1 104 the inductor LVcc1 106. The resistor RVcc1 104 represents the cumulative resistance of the wiring within the ASIC used to distribute the power supply voltage Vcc to the core logic section 110. The inductor LVcc 106 represents the inductance of the cumulate wiring within the ASIC used to distribute the power supply voltage Vcc to the core logic section 110.
The return of the power supply voltage Vss through the Vss pad 120 is modeled by the resistor RVss1 116 and the inductor LVss1 118. The resistor LVss1 116 and the inductor LVss1 118 represent respectively the distributed resistance and inductance of the wiring used to distribute the return of the power supply voltage Vss from the core logic section 110. The return of the power supply voltage Vss is often a common or ground reference point with the system containing the ASIC.
The capacitance Ccore 112 represents the capacitance of the circuitry of the core logic section 110 between the first power supply voltage node Vcc1 108 and the first return node Vss1 114 of the power supply voltage.
A similar structure is present at the peripheral logic section 138. The resistor RVcc2 132 and the inductor LVcc2 134 model the distribution wiring from the Vcc pad 106 and the peripheral logic section 138. The resistor RVss2 146 and the inductor LVss2 148 model the distribution wiring of the return of the power supply Vss from the peripheral logic section 138 and the Vss pad 122.
The capacitor Cperi represents the capacitance of the circuitry of the peripheral logic section 138 between the second power supply node Vcc2 136 and the second return node Vss 2 142 of the power supply voltage.
The first and second return nodes are generally connected to the semiconductor substrate on which the ASIC is constructed. However, the core logic section and the peripheral logic section may be constructed in a well having a doping of an impurity of a polarity opposite of the doping of the impurity of the semiconductor substrate. This would be an n-well on a p-type substrate or a p-well on an n-type substrate. This will further isolate the return nodes Vss1 114 and Vss2 142 from each other.
While the core logic section 110 and the peripheral logic section 138 were described above as having a common power supply voltage source Vcc, often the core logic section 110 has a power supply voltage source of a different voltage level than the peripheral logic section 138. The peripheral logic section may have a power supply voltage source Vcc of 5.0V and the core logic section may have a power supply voltage source Vcc of 3.3V. Further, ASIC implementations may have multiple core logic sections and multiple peripheral logic sections, as well as analog core sections. Each section will have a separate voltage distribution network for the power source, and return paths. The models for these voltage distribution networks is as described above.
An ESD event is commonly a pulse of a very high voltage typically of several kilovolts with a moderate current of a few amperes for a short period, typically about 100 nanoseconds. The common sources of an ESD event is bringing the ASIC in contact with a human body or a machine such as an integrated circuit tester and handler.
If the I/O pad 140 is contacted and subjected to an ESD event, the second power supply node Vcc2 136 and the second return node Vss2 will begin to change relative to the voltage level of the power supply voltage source Vcc. This change can cause damage in subcircuits that form an interface between the core logic section 110 and the peripheral logic section 138. xe2x80x9cNovel Clamp Circuits for IC Power Supply Protection,xe2x80x9d Maloney et al., Proceedings EOS/ESD Symposium, 1995, pp. 1.1.1-1.1.12, Dabral et al., and U.S. Pat. No. 5,616,943 (Nguyen et al.) describe implementations clamp circuits 124 and 130. The clamp circuits prevent a differential voltage developed between the first power supply node Vcc1 108 and the second power supply node Vcc2 136 or from the first return node Vss 1 114 and the second return node Vss 2 142 from exceeding a clamp voltage. The clamp voltage is larger than the maximum allowable voltage difference between the first power supply node Vcc1 136 and the second power supply node Vcc2 136, but less than a breakdown voltage that causes damage to the subcircuits that create the interface between the core logic section 110 and peripheral logic circuit 138.
FIG. 2 shows a schematic of the clamp circuits 124 and 130 of Dabral et al., Maloney et al., and Nguyen et al. The clamp circuit 124 and 130 is connected between a first power supply terminal Vx1 200 and a second power supply terminal Vx2 205. The diodes D11 210, D12 215, . . . , D1m 220 are serially connected together, cathode to anode to form a diode chain. The cathode of the first diode D11 210 is connected to the first power supply node Vx1 200. The anode of the first diode D11 210 is connected to the cathode of the next subsequent diode D12 215. The anode of the last diode D1m 220 is connected to the second power supply node Vx2 205, while its cathode is connected to the anode of the next subsequent diode.
The diode chain D21 235, D22 230, . . . , D2m 225 are similarly connected between the second power supply node Vx2 205 and the first power supply node Vx1 220. The cathode of the first diode D21 235 is connected to the second power supply node Vx2 205, and the anode of the last diode D2m 225 is connected to the first power supply node Vx1 200.
If the voltage at the power supply node Vx2 205 rises above the total voltage required for the diode chain D11 210, D12 215, . . . , D1m 220 to conduct relative to the voltage Vx1 200, the diode chain D11 210, D12 215, . . . , D1m 220 will conduct, clamping the voltage between the second power supply node 205 and the first power supply node 210 to the voltage level across the diode chain D11 210, D12 215, . . . , D1m 220.
Conversely) if the voltage at the power supply node Vx1 200 rises above the total voltage required for the diode chain D21 235, D22 230, . . . , D2m 225 to conduct relative to the voltage Vx2 205, the diode chain D21 235, D22 230, . . . , D2m 225 will conduct, clamping the voltage between the first power supply node Vx1 200 and the second power supply node 205 to the voltage level across the diode chain D21 235, D22 230, . . . , D2m 225.
The clamping voltage between the first power supply node Vx1 200 and the second power supply node Vx2 205 is determined by the diode voltage drop of each diode in the diode strings. The differential voltage between the first power supply node Vx2 205 should be greater than the differences in the operating voltages of the first power supply node Vx1 200 and the second power supply node Vx2 205, but less than the voltage that can cause damage in subcircuits in the interface between the core logic section 110 and the peripheral logic section 138.
Refer now to FIG. 3 for a discussion of the physical structure of a diode string as implemented on a p-type semiconductor substrate 300. The N-wells 305a, 305b, . . . , 305M are diffused to a lightly doped concentration into the surface of the p-type semiconductor substrate 300 to form the cathode of the diodes DX1 350a, DX2 350B, . . . , DXm 350m. The N+ contacts 310a, 310b, . . . , 310m are diffused to a highly doped concentration into the N-wells 305a, 305b, . . . , 305m. 
A p-type material is diffused into the N-wells 305a, 305b, . . . , 305m to a highly doped concentration to form the p+ contacts 315a, 315b, . . . , 315m. The p+ contacts 315a, 315b, . . . , 315m are the anodes of the diodes DX1 350a, DX2 350B, . . . , DXm 350m. 
The anode 315a of the first diode DX1 350 in the diode chain is connected to the first power supply terminal 320. The cathode 310a of the first diode Dx1 350 in the diode chain is connected 360 to the anode 315b of the next subsequent diode Dx2 350b. Each subsequent diode is connected cathode to anode to form the chain of diodes DX1 350a, DX2 350B, . . . , DXm 350m. The cathode 310m of the last diode DXm 350m is connected to:the second power supply voltage terminal V2 325.
Generally, the p-type semiconductor substrate 300 is connected to the return node Vss 330 of the power supply. This structure creates a parasitic PNP clamping transistor for each diode of the diode chain DX1 350a, DX2 350B, . . . , DXm 350m. The parasitic PNP are now connected as a Darlington string of transistors. As is shown in Maloney et al., the gain of the Darlington string results in a loss of forward current to the p-type substrate 300 and thus reducing the voltage across the xe2x80x9cdownstreamxe2x80x9d diodes and increasing the current requirement for a given voltage. Further, the Darlington string amplifies the junction leakage of the xe2x80x9cdownstreamxe2x80x9d N-wells 305m, thus causing excess currents from the first power supply voltage terminal V1 320 and the second power supply voltage terminal V2 325.
U.S. Pat. No. 5,073,591 (Chen et al.) discloses an electrostatic discharge circuit. Small electrostatic voltages are used to generate charged carriers, which are used to trigger Schottky clamp diode, thereby limiting the electrostatic voltages to magnitudes significantly less than a one hundred volt breakdown. A vertical bipolar trigger transistor is formed in the semiconductor substrate adjacent the Schottky diode. The bipolar transistor is fabricated in a common emitter configuration so that it exhibits a low breakdown voltage. When the voltage of the electrostatic discharge reaches about twenty volts, the emitter-base junction of the trigger transistor becomes forward biased and the base-collector junction becomes reverse biased. The electrons and the holes generated by the avalanche breakdown of the reverse biased base-collector junction are attracted to the Schottky diode, thereby prematurely turning it on before it is driven breakdown by a much higher electrostatic voltage.
In the preferred form of Chen et al., the bipolar transistor is of PNP type. In addition, the trigger transistor is formed with the base the trigger transistor connected to a supply voltage input terminal of the integrated circuit. In this manner during normal powered operations of the circuit, any overshoot or transient voltage appearing on the input is damped to a low voltage, thereby preventing latch-up. In CMOS and MOSFET circuits, latch-up is an undesirable characteristic which can occur during power up of the circuit, or as a result of. input voltage overshoots which can drive inherent parasitic SCR""s into a latched state. However, during electrostatic discharge to the input, the trigger transistor is not biased by the supply voltage, but rather is biased to a higher voltage by an inherent Zener diode formed by the overall integrated circuit which is also connected to the supply voltage terminal. Chen et al. has the technical advantage of the biasing arrangement is that both latch-up immunity and electrostatic discharge protection are enhanced.
U.S. Pat. No. 5,442,217 (Mimoto) discloses a semiconductor apparatus including an electrostatic discharge protection device. The semiconductor apparatus includes a plurality of NPN transistors. The base of the NPN transistors is effectively the semiconductor substrate. The N-type diffusion of the NPN transistors forming the collector and emitter is placed under each pad of the integrated circuit constructed on the semiconductor substrate. Further, the N-type diffusion creates diodes between each pad and the semiconductor substrate. Either an electrostatic discharge greater than the operation voltages of the integrated circuit will cause the transistors or the diodes will breakdown causing the discharge currents to flow to the semiconductor substrate.
U.S. Pat. No. 5,290,724 (Leach) discloses an electrostatic discharge protection circuit between two bond pads of an integrated circuit on a semiconductor substrate. The electrostatic discharge protection circuit is group of cascaded bipolar transistors connected in series with a field effect transistor between two bond pads.
A second form of the invention of Leach discloses an output buffer that is divided into two sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one bond pad. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit.
U.S. Pat. No. 4,990,976 (Hattori) teaches a semiconductor device having a field effect transistor and a protective diode in parallel. The breakdown voltage of the protective diode can be altered without changing the threshold voltage of the field effect transistor. Further, the protective diode may be a Zener diode and is constructed to prevent latch-up.
U.S. Pat. No. 5,159,518 (Roy) describes an input circuit for the protection of MOS semiconductor circuits from ESD discharge voltages and from developing circuit latch-up. The input protection circuit includes and low resistance input resistor and a pair of complementary true gated diodes. Roy describes a true gated diode as a MOS structure having a gate and a drain but no source. Each true gated diode has an associated vertical parasitic bipolar transistor, which helps dissipate an Electrostatic Discharge. However, the true gate diode does not have a lateral parasitic bipolar transistor under the gate oxide. This reduces the amount of stress during an ESD event on the gated diode""s gate oxide.
U.S. Pat. No. 5,208,719 (Wei) teaches a circuit that protects MOS circuits connected to an output pad of an integrated circuit from ESD, whether or not the output pad is connected to a power supply or mounted on a printed circuit board. The circuit includes a PMOS transistor connected such that the output transistor is turned on when positive ESD is present. The output NMOS transistor safely dissipates ESD current and does not enter the destructive xe2x80x9csnapbackxe2x80x9d mode. The circuit of Roy protects the CMOS device even when it is not connected to a power supply or other devices.
U.S. Pat. No. 5,287,241 (Puar) teaches a circuit is added to a complementary metal-oxide silicon (CMOS) integrated circuit (IC) to provide an intentional, non-reversed biased VDD to VSS shunt path for transient currents such as ESD. This circuit protects the IC from ESD damage by turning on before any other path, thus directing the ESD transient current away from any easily damaged structures. Specifically, the ESD transient current is steered away from the VDD rail to the VSS rail through the on conduction of a P-channel transistor whose source and drain are connected to VDD and VSS respectively. The voltage on the-gate of this transistor follows the VDD supply rail because it is drive by a delay network formed by a second transistor and a capacitor. This VDD-tracking network turns the VDD-to-VSS transistor on during a transient and off during normal operation of the IC.
U.S. Pat. No. 5,274,262 (Avery) describes an integrated circuit device to protect integrated circuits from ESD transient currents. The device is an SCR having a reduced xe2x80x9csnapbackxe2x80x9d trigger voltage. The SCR protection circuit has a first and second bipolar transistors. The emitter of the first bipolar transistor connected to a first terminal of the circuit and to the collector of the second bipolar transistor. The base of the first bipolar transistor is connected to the collector of the second bipolar transistor. The collector of the first bipolar transistor is connected the base of the second bipolar transistor and to a second terminal. The emitter of the second bipolar transistor is connected to the second terminal. The means for reducing the trigger voltage of the SCR is connected between the bases of the first bipolar transistor and the second bipolar transistor.
U.S. Pat. No. 5,087,955 (Futami) describes a peripheral block of a semicustom integrated circuit. The peripheral block has an N-channel MOS transistor formed in close proximity to an input/output pad on a semiconductor substrate. The input/output pad has a wiring conductor connected to internal circuitry on the semiconductor substrate and to the drain of the N-channel MOS transistor. The gate and source of the N-channel MOS transistor is connected to ground. In this configuration, the N-channel MOS transistor acts as a protection diode to protect the internal circuits from transient ESD voltages. P-channel MOS transistors additionally may be connected to the input/output pad to provide paths not only to ground, but also to any power supply voltage sources on the semiconductor substrate.
An object of this invention is to provide an ESD protection circuit that will protect integrated circuits having multiple separate power supply voltage terminals from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage terminals.
To accomplish this and other objects a voltage clamping circuit is connected between a first power supply voltage terminal and a second power supply voltage terminal to prevent a differential voltage developed between the first power supply terminal and the second power supply terminal from exceeding a first clamping voltage level and a second clamping voltage level. The second clamping voltage level being equal in magnitude and opposite in polarity to the first clamping voltage level. The voltage clamping circuit has two subgroups of Darlington connected clamping transistors. The first subgroup of Darlington connected clamping transistors is connected between the first power supply voltage terminal and the second power supply voltage terminal. If the differential voltage exceeds the first clamping voltage level, the first subgroup of Darlington connected clamping transistors turn on and restore the first differential voltage to a level less than the first clamping voltage level. The second subgroup of Darlington connected clamping transistors connected between the second power supply terminal and the first power supply terminal. Conversely, if the differential voltage exceeds the second clamping voltage level, the second subgroup of Darlington connected transistors turn on and restore the differential voltage to a level less than the second clamping voltage level.
Each subgroup of Darlington connected transistors include a first transistor, a plurality of subsequent transistors, and a last transistor. The first transistor has a base and collector connected to the first power supply voltage terminal and an emitter connected to a base of one of a subsequent adjacent transistors. The plurality of subsequent transistors each transistor has a collector connected to the first power supply terminal, an emitter connected to the base of the subsequent adjacent transistor. The last transistor has a collector connected to the first power supply terminal, a base connected to an emitter of a previous subsequent transistor and an emitter connected to the second power supply terminal.
The number of clamping transistors in the first subgroup and the second subgroup of Darlington connected clamping transistor is determined by the formula:   n  ≥                    V        noise            +              "LeftBracketingBar"                  Vcc1          -          Vcc2                "RightBracketingBar"                    V      T      
where:
n is the. number of clamping transistors in the first and second subgroups of Darlington connected clamping transistor,
Vnoise is the voltage level of the circuit noise present on the internal circuits of the integrated circuit,
Vx1 is the first power supply voltage source connected to the subgroup of Darlington connected clamping transistors,
Vx2 is the second power supply voltage source connected to the subgroup of Darlington connected clamping transistors, and
VTis the threshold voltage of each of the clamping transistors.
Each clamping transistor of the first and second subgroup of Darlington connected transistor is fabricated with a collector well of a first conductivity type having a first concentration diffused in a surface of a semiconductor substrate. At least one collector contact region of the first conductivity type having a second concentration that is greater than the first concentration is then diffused into the surface of the semiconductor substrate within the collector well to form a first low resistivity contact to the collector well. A base well of a second conductivity type, having a third concentration is diffused into the surface of the semiconductor substrate within the collector well. Within the base well, a base contact of the second conductivity type, having a fourth concentration that is greater than the third concentration is diffused into the surface of the semiconductor substrate to form a second low resistivity contact to the base well. Finally, an emitter region of the first conductivity type of the second concentration is then diffused into the surface of the semiconductor substrate within the base well separated from the base contact.